一种改进型的CMOS电荷泵锁相环电路  

An Improved CMOS Charge Pump PLL Circuit

作　　者：李演明[1] 仝倩[1] 倪旭文 邱彦章[1] 文常保[1] 吴凯凯[1] 柴红[1] 

机构地区：[1]长安大学电子与控制工程学院微纳电子研究所,西安710064

出　　处：《半导体技术》2014年第4期248-253,共6页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60806043);西安布科技计划资助项目(CXY1342(6));中央高校基本科研业务费资助项目(2013G1321041;2013G3322010)

摘　　要：设计了一种宽频率范围的CMOS锁相环(PLL)电路,通过提高电荷泵电路的电流镜镜像精度和增加开关噪声抵消电路,有效地改善了传统电路中由于电流失配、电荷共享、时钟馈通等导致的相位偏差问题。另外,设计了一种倍频控制单元,通过编程锁频倍数和压控振荡器延迟单元的跨导,有效扩展了锁相环的锁频范围。该电路基于Dongbu HiTek 0.18μm CMOS工艺设计,仿真结果表明,在1.8 V的工作电压下,电荷泵电路输出电压在0.25~1.5 V变化时,电荷泵的充放电电流一致性保持很好,在100 MHz^2.2 GHz的输出频率内,频率捕获时间小于2μs,稳态相对相位误差小于0.6%。A CMOS phase-locked loop （PLL） with a wide range of frequencies was presented, the phase errors arising from current mismatching in charge pump circuit, charge sharing and clock feed- through was corrected effectively by increasing the current mirror accuracy and decreasing the switching noise in the traditional charge pump circuit. In addition, a multiplier control unit was adopted to set the multiples of the output frequency and transconduetance of VCO＇s delay unit, expanding effectively the PLL＇s locking range. Based on Dongbu HiTek 0. 18 μm CMOS process, the simulation results show that when the output voltage of the charge pump circuit varies between 0.25 V and 1.5 V with 1.8 V supply voltage, the charge and discharge currents of charge pump can maintain excellent matching, and within 100 MHz-2.2 GHz output frequency range, the proposed PLL circuit can synchronize with locking time below 2 μs and the relative phase error is less than 0.6%.

关 键 词：锁相环 电荷泵 鉴频鉴相器 压控振荡器 互补金属氧化物半导体(CMOS ) 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN402