一种降低并行ADC非线性误差的电容平均技术  

Capacitor averaging technology for reducing the non-linearity offset in parallel ADC

作　　者：熊莉英[1] 郭颖[1] 李家会[1] 朱正为[1] 

机构地区：[1]西南科技大学信息工程学院,四川绵阳621010

出　　处：《电子技术应用》2014年第4期35-38,共4页Application of Electronic Technique

基　　金：国家自然科学基金(61105020)

摘　　要：提出了一种降低并行ADC中比较器失调的电容平均网络。该网络由比较器的输入失调存储电容和平均电容构成。通过理论推导和ADC系统级仿真,当平均电容与输入失调存储电容取值相等时,电容平均网络可以有效抑制70%以上的INL误差和DNL误差。This paper presents a circuit design using an integrating capacitance network to reduce offset of comparators in Flash ADC. This network consists of input offset storage capacitors of comparators and averaging capacitors. Through theoretical derivation and ADC system simulation, when the average capacitance and input offset storage capacitance values are equal, the differential non-linearity （DNL） offset and the integral non-linearity（INL） offset are reduced more than 70% by applying this capacitance offset averaging network.

关 键 词：模 数转换器 比较器失调 非线性误差 失调平均技术 电容平均网络 

分 类 号：TM134[电气工程—电工理论与新技术]