可配置并行HEVC去块滤波VLSI设计  

Configurable and parallel VLSI design for deblocking filter of HEVC

作　　者：路伟[1] 余宁梅[1] 南江涵 王冬芳[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,陕西西安710048

出　　处：《西安理工大学学报》2014年第1期46-51,共6页Journal of Xi'an University of Technology

基　　金：陕西省自然科学基础研究计划基金资助项目(2011JQ8032);陕西省重点学科建设专项资金资助项目(107080903)

摘　　要：提出了一种滤波单元数可配置的HEVC去块滤波器VLSI结构。通过对HEVC的去块滤波算法分析,针对滤波块间相互独立进行滤波的特性,设计了滤波单元数可配置的并行结构。该结构将滤波单元设计成基本单元,数量可调节。在提高了吞吐率和计算效率的同时,解决了VLSI设计中面积过大的问题。并设计了转置模块,有效地对数据进行调整,以提高流水线运行效率。在SMIC 0.13μm工艺库下,进行逻辑综合,滤波单元采用4个,系统总门数为59.7K。在时钟频率300MHz下,可处理3840×2160@33fps的视频序列。A parallel and configurable VLSI architecture for deblocking filter of HEVC is proposed in this paper.By reference software algorithm of HEVC analysis,independently of each other for the filter characteristic between the filtering block,the filter unit number configurable parallel structure is designed.This structure of filtering unit is designed to be a substantially unit,and number can be configured.While the calculation efficiency and throughput are being improved,the problem of the area that is too large in the design of VLSI has been solved.And the transposition module is designed so as to adjust the data effectively and to improve the efficiency of the pipeline.After logic synthesis using SMIC0.13μm standard cell library,four filter units are used and the number of gates is 59.7 K.This design can handle 3840×2160@33 fps under the working frequency of 300 MHz.

关 键 词：去块滤波 高效图像编码 可配置 

分 类 号：TN47[电子电信—微电子学与固体电子学]