IEEE802.15.4时隙CSMA/CA算法性能研究  

Research on Performance of Slot CSMA/CA Algorithm in IEEE802.15.4

作　　者：姜智文[1] 周熙[1] 佘阳[1] 黄磊[1] 李广位[1] 

机构地区：[1]重庆通信学院,重庆400035

出　　处：《无线电通信技术》2014年第2期34-37,共4页Radio Communications Technology

摘　　要：对IEEE802.15.4标准和时隙CSMA/CA算法进行了简单介绍,基于OPNET仿真软件,针对节点个数、工作周期(占空比)等参数对时隙CSMA/CA算法性能的影响,进行了不同网络环境的仿真实验。分别在固定节点个数和固定占空比条件下,仿真并分析了介质接入时延与吞吐量及网络能耗之间的关系。仿真结果表明,较多的节点个数和较小的工作周期会增大介质接入时延,降低网络吞吐量。In this paper,the IEEES02.15.4 standard and slot CSMA/CA algorithm are simply introduced. We study and discuss the impact of number of nodes and duty cycle on the slotted CSMA / CA algorithm performance based on OPNET simulation software under different network conditions through simulation experiments. The relationship among media access delay, network throughput and energy consumption are simulated and analyzed with fixed number of nodes and a fixed duty respectively. Simulation results demonstrate that more number of nodes and a smaller duty cycle lead to increases in the media access delay and reduced network throughput.

关 键 词：介质接入时延 吞吐量 能耗 时隙CSMA CA算法 IEEE802 15 4 

分 类 号：TN391.4[电子电信—物理电子学]