基于FPGA的二维DCT／IDCT高速设计与实现  

The High Speed Design and Implementation of 2-Dimensional DCT/IDCT Based on FPGA

作　　者：苏阳[1] 

机构地区：[1]武警工程大学电子技术系,陕西西安710086

出　　处：《武警工程大学学报》2014年第2期38-42,共5页Journal of Engineering University of the Chinese People＇s Armed Police Force

基　　金：武警工程大学2013年基础研究基金资助项目（WJY201312）

摘　　要：二维离散余弦／反余弦变换是图像处理算法的核心。基于DSP处理器或软件实现速度较低，以及ASIC实现芯片的面积和功耗都较大，本文研究了一种基于行列分解结构的二维DCT／IDCT变换，在两级一维DCT／IDCT变换之间插入双RAM结构，通过乒乓操作保证了前后级DCT／IDCT运算的并行性，提高了运算速度。电路结构在QuartusII中进行了逻辑综合，通过Modelsim编写激励对逻辑功能进行了仿真验证，并将仿真结果与Mat—lab仿真结果进行了比较。结果表明该模块功能正确，能够为图像处理提供良好的处理性能。The two-dimensional discrete cosine/inverse cosine transform is the core of the im- age processing algorithm. The speed of DSP processor or software is low, and the chip area and power consumption of ASIC are large. This paper studies a row-column decomposition structure of two-dimensional DCT/IDCT transform based on inserting the double RAM structure into the two levels of one-dimensional DCT/IDCT transform, the ping-pong opera- tion ensures the parallelism of DCT/IDCT and improves the speed of computation. The logic synthesis of the circuit structure is done in Quartus II and the logic function is simulated in Modelsim through writing excitation, and the simulation results are comparted with the Mat- lab simulation results. The results indicate that the module function is correct, and can provide good performance for image processing.

关 键 词：二维离散余弦变换 二维离散余弦反变换 现场可编程门阵列 行列分解结构 高速设计 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]