一种全数字半速率鉴相器的设计  

Design of all-digital half-rate phase detector

作　　者：邓军勇[1] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《现代电子技术》2014年第9期145-147,153,共4页Modern Electronics Technique

基　　金：国家自然科学基金(61136002;61272120);陕西省教育厅专项科研计划(2010JK817)

摘　　要：鉴相器是高速时钟数据恢复环路的关键电路,其性能的优劣直接影响了整个系统的工作。通过系统分析,提出了一种全数字半速率鉴相器设计方案,按照全定制设计流程采用SMIC 0.18μm CMOS混合信号工艺完成了电路的设计、仿真。结果表明该电路在2.5 Gb/s收发器电路中可以稳定可靠地工作。The phase detector is a critical part of high-speed clock and data recovery circuit. Its performance has great influence on the whole system. According to a system analysis,a design scheme of all-digital half-rate phase detector is proposed in this paper. According to the full custom design flow,the circuit design and simulation were accomplished with the process of SMIC 0.18 μm CMOS mixed-signal. The simulation result shows that the circuit can work stably in the 2.5 Gb/s transceiver circuit.

关 键 词：CMOS电路 鉴相器 半速率结构 混合信号 

分 类 号：TN473.4[电子电信—微电子学与固体电子学]