高速低相差双路AD数据采集器的设计  

The Design of A High Speed AD Data Acquisition with Low Phase Delay

作　　者：丁喜冬[1] 薛淑军[2] 龚康[1] 

机构地区：[1]中山大学物理学系,广东广州510275 [2]中山大学电子机械研究中心,广东广州510275

出　　处：《中山大学学报（自然科学版）》2001年第1期29-31,共3页Acta Scientiarum Naturalium Universitatis Sunyatseni

基　　金：国家自然科学基金资助项目(19974077);广东省攻关资助项目(99M01007G)

摘　　要：介绍一种高速低相差双路ＡＤ数据采集器．通过使用比要求的采样速度更高速的ＡＤＣ及对两路ＡＤＣ进行严格的同步控制等措施，设计出的ＡＤ数据采集器具有相位抖动小于１个采样周期，并与采样速度无关，且对接口速度要求低。接口硬件简单等特点．实验表明，对频率为５Ｈｚ的模拟输入信号，其相位分辨率可达 ５ × １０－５ｒａｄ．A high speed Analog-to-digital data acquisition with low phase delay between two channels is intro-duced. By using the AD converter with a higher speed than that of data acquisition, all of the synchronous signals are controlled strictly. The designed AD data acquisition has many advantages such as a phase delay smaller than a single acquisition period regardless of the acquisition speed, and a novel interface which demands low speed and simple hardware. Experiments show that the phase delay is about 5 x 10-i radian when the input analog signal fre-quence is 5 Hz.

关 键 词：相位差 固体内耗仪 采样速度 高速低相差双路AD数据采集器 设计 采样周期 相位分辨率 

分 类 号：TP274.202[自动化与计算机技术—检测技术与自动化装置]