基于FPGA的高精度正弦信号发生器设计与实现  

FPGA based high precision sinusoidal signal generator

作　　者：彭卓[1,2] 邓焱[1] 马骋[1] 熊剑平[1] 尹永利[2] 

机构地区：[1]清华大学精密仪器系,精密测试技术及仪器国家重点实验室,北京100084 [2]中国航天员科研训练中心,北京100094

出　　处：《清华大学学报（自然科学版）》2014年第2期197-201,共5页Journal of Tsinghua University(Science and Technology)

摘　　要：地震数据采集系统自检时需要总谐波失真小于-106dB的高保真正弦信号,一般采用24位ΔΣ数模转换器来产生,关键技术是如何生成驱动ΔΣ数模转换器的位流。该文提出一种由正弦数据存储器、插值滤波器和ΔΣ调制器组成的位流生成器,重点介绍了插值滤波器和ΔΣ调制器的设计思路、仿真方法及其在现场可编程门阵列(FPGA)中借助DSP Builder工具实现的方法。实测结果表明:该位流生成器可以驱动一块ΔΣ数模转换器产生31.25Hz、峰峰值3.96V的高保真正弦信号,信噪比达到111.4dB,总谐波失真达到-121.0dB,满足地震数据采集系统自检的要求,并且具有结构简单、可编程和开发周期短的优势。A 24-bit sigma-delta digital-to-analog converter （DAC） is used to produce high precision sinusoidal signals with low total harmonic distortion （usually less than - 106 dE） for seismic data acquisition system self-tests. The key problem is to convert the sinusoid to a sigma-delta bit stream to drive the sigma-delta DAC. This paper presents a field-programmable gate array （FPGA） based bit stream generator which is composed of a sinusoidal data memory, an interpolation filter and a sigma-delta modulator. This paper focuses on the design and simulation methods for the interpolation filter and the sigma-delta modulator and the whole system implementation using the DSP Builder in FPGA. Tests show that the bit stream generator can drive a 24-bit sigma-delta DAC to produce a 31.25 Hz, 3.96 V peak-peak voltage sinusoidal signal with - 121.0 dB total harmonic distortion and 111.4 dB signal-to-noise ratio, which meets the needs for seismic use. The design is simple,programmable and easy to implement.

关 键 词：地震数据采集 正弦信号发生器 △∑调制器 现场可编程门阵列(FPGA) 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]