LOW-POWER SURVIVOR MEMORY ARCHITECTURE FOR DFSE IN 1000BASE-T TRANSCEIVER  

作　　者：Qiu Bingsen 

机构地区：[1]2012 Laboratories,Huawei Technologies Co.Ltd

出　　处：《Journal of Electronics(China)》2014年第2期92-99,共8页电子科学学刊（英文版）

摘　　要：A novel approach to survivor memory unit of Decision Feedback Sequence Estimator(DFSE) for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed.The proposed architecture is investigated with special emphasis on low power and small decoder latency,in which a dedicated register-exchange module is designed to provide tentative survivor symbols with zero latency,and a high-speed trace back logic is presented to meet the tight latency budget specified for 1000BASE-T transceiver.Furthermore,clock-gating register banks are constructed for power saving.VLSI implementation reveals that,the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.A novel approach to survivor memory unit of Decision Feedback Sequence Estimator （DFSE） for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed. The proposed architecture is investigated with special emphasis on low power and small decoder latency, in which a dedicated register-exchange module is designed to provide tentative survivor syml^ols with zero latency, and a high-speed trace back logic is presented to meet tile tight latency budget specified for 1000BASE-T transceiver. Furthermore, clock-gating register banks are constructed for power saving. VLSI implementation reveals that, the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.

关 键 词：Survivor memory unit Register exchange Trace back Decision Feedback Sequence Estimator(DFSE) 1000BASE-T 

分 类 号：TN492[电子电信—微电子学与固体电子学] TN911.23