Design of Low-Power Modern Radar SoC Based on ASIX  

作　　者：Bing Yang Zongguang Yu Jinghe Wei 

机构地区：[1]Schoolol of Internetof Things Engineering,Jiangnan University [2]China Electronics Technology Group Corporation No.58 Research Institute

出　　处：《Tsinghua Science and Technology》2014年第2期168-173,共6页清华大学学报（自然科学版（英文版）

基　　金：funded by the "333 Engineering" Assistance Project of Jiangsu Province,China (No. BRA2011115)

摘　　要：With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.With the rapid development in spaceflights and aeroplanes, the demand for low-power and miniaturization techniques has become insistent in modern radar systems. A new framework for low-power modern radar System on a Chip （SoC） based on ASIX core is presented. Pivotal modules and low-power design flows are described in detail. The dynamic clock-distribution mechanism of the power management module and the influence of the chip power are both stressed. This design adopts the SMIC 0.18-μm 1P6M Salicide CMOS process, the area is 7.825 mm x 7.820 mm, there are approximately 2 million gates and the frequency is 100 MHz. The results show that the modern radar SoC passes the test on modern radar application system and meets the design requirements. The chip incurs power savings of 42.79% during the fore-end phase and 12.77% during the back-end phase. The total power is less than 350 mW for a 100-MHz operating environment.

关 键 词：ASIX core System on a Chip （SoC） low power system level circuit level logic level physical level modern radar 

分 类 号：TN952[电子电信—信号与信息处理]