2 GHz采样连续时间ΣΔ ADC高层次建模  

High Level Modeling of a 2 GHz Sampling Continuous-TimeΣΔ A/D Converter

作　　者：袁俊[1] 杨银堂[1] 张钊锋[2] 朱樟明[1] 

机构地区：[1]西安电子科技大学微电子学院,西安710071 [2]中国科学院上海高等研究院,上海201203

出　　处：《微电子学》2014年第2期260-263,272,共5页Microelectronics

基　　金：国家重大专项资助项目(2010ZX03006-003-02)

摘　　要：宽带连续时间ΣΔADC被大量应用于无线通信及其他领域。设计采用3阶连续时间系统架构,包含3级RC环路滤波器和4位内部量化器,采样时钟频率为2GHz。通过引入半个时钟周期延时来改善环路异步问题,以补偿环路延时对性能的影响。对连续时间ΣΔADC的非理想因素,如运放有限带宽、有限增益、积分器时常数变化、DAC失配、比较器失调、时钟抖动等,进行建模,通过大量系统仿真,得出各个非理想参数指标,在100 MHz带宽内、2GHz采样频率下,ΣΔADC的SNDR为76.8dB,动态范围为77dB。A framework for behavioral simulation of continuous time sigma delta（CTSD）modulator developed in Matlab/Simulink was presented.Error sources in CTSD design were reviewed and it was explained how sub-module specifications could be derived from a system-level target performance.A CTSD modulator was designed as an example to illustrate the results and error models.The 3rd-order continuous timeΣΔ modulator consisted of a 3rdorder RC loop filter based on operational amplifier and 4-bit internal quantizer operating at 2GHz clock frequency. Non-return-to-zero（NRZ）DAC pulse shaping was used to reduce clock jitter sensitivity.The excessive loop delay was set to half the sampling period of the quantizer,and the degradation of modulator stability due to excessive loop delay was avoided with this architecture.TheΣΔADC achieved an SNDR of 76.8dB and a dynamic range of 77dB over a 100MHz signal band at an OSR of 10with 2GHz sampling frequency.

关 键 词：模数转换器 连续时间 高层次建模 

分 类 号：TN792[电子电信—电路与系统]