一种基于FPGA的PWM脉冲发生器设计  

The Design of a PWM Pulse Generator Based on FPGA

作　　者：俞晨光[1] 席自强[1] 李开成[1] 周世平[1] 

机构地区：[1]湖北工业大学电气与电子工程学院,湖北武汉430068

出　　处：《湖北工业大学学报》2014年第2期48-51,共4页Journal of Hubei University of Technology

摘　　要：针对级联多电平静止同步补偿装置,采用基于不对称规则采样的SPWM脉冲的生成方法,并研制了基于可编程逻辑门阵列(FPGA)实现的PWM脉冲发生器。以级联多电平3链节H桥静止同步补偿发生器(STATCOM)为例,分析了不对称规则采样的脉冲生成方式,介绍脉冲发生器的基本原理和结构以及实现方法。在保证输出电压波形不对称性得到改善的同时,该PWM发生器也简化了电路的设计,提高了系统的可靠性。Aiming at cascade multilevel static reactive compensation device,this paper presents a SPWM pulse generating method based on asymmetry regular sampling,and has developed a PWM pulse generator depending on the field programmable logic gate array（FPGA）.Take multilevel cascade H bridge static synchronous compensation generator as an example,it first analyzed the pulse generating method of the asymmetry regular sampling,then introduced the basic principle and structure of the pulse generator and its implementation method.This PWM generator guarantees the asymmetry of the output voltage waveform being improved,simplifies the circuit design and also improves the reliability of the system.

关 键 词：级联H桥 多电平静止同步补偿发生器 现场可编程门阵列器件 

分 类 号：TM464[电气工程—电器]