基于FPGA的三维视频系统实时深度估计  

FPGA-based real-time depth estimation for 3D video system

作　　者：李贺建[1] 安平[1] 张兆杨[1] 王奎[1] 程浩[1] 

机构地区：[1]上海大学新型显示技术及应用集成教育部重点实验室、通信与信息工程学院,上海200072

出　　处：《光电子．激光》2014年第5期974-980,共7页Journal of Optoelectronics·Laser

基　　金：国家自然科学基金(61172096,U1301257);上海市科学技术委员会重点项目(10510500500,12dz1500401)资助项目

摘　　要：深度估计是基于视频加深度图像的三维视频系统中前端预处理的核心技术,其主要技术难题包括准确性、实时处理和大分辨率深度图获取等。本文提出一种实时深度估计的硬件实现方案,主要解决处理速度问题,并兼顾了准确性和大分辨率问题。本方案采用单片FPGA实现深度估计,其中采用census变换与SAD(Sum of Absolute Differences)混合的算法进行逐点匹配得到稠密深度图。硬件设计充分利用FPGA的大规模并行能力,并采用流水线设计提高数据通路的数据吞吐量,提升整个设计的时钟频率。实验表明,所提出的方案可实现全高清(1 920×1 080)分辨率视频实时深度估计。为了支持大分辨率图像并能观测距离相机较近的物体深度,本文方案视差搜索范围可以达到240pixels,帧率最高可达69.6fps,达到了实时和高清的处理目的。Depth estimation is one of the key techniques in the front-end of stereoscopic waeo system which still faces some challenges, such as the depth accuracy, real-time processing and high resolution depth map generation. This paper proposes a hardware solution for real-time depth estimation to mainly resolve the speed issue,the accuracy as well as the high resolution- The system is implemented on a sin- gle FPGA, which uses match algorithm mixed by census transform and sum of absolute differences （SAD） to obtain a dense depth map. The design makes full use of the massive parallel resources and pipeline architectures of FPGA to improve data through-out and system clock frequency. Experiment re- sults show that the proposed method is reasonable.and can achieve real-time depth estimation for the full high definition （HD） （1920×1080）resolution video, with the disparity search range up to 240 pixels and the frame rate up to 69.6 frame/sl The performance of the proposed hardware system meets the require- ments of 3D video system.

关 键 词：三维视频 实时性 深度估计 

分 类 号：TN919.81[电子电信—通信与信息系统]