A high speed multi-level-parallel array processor for vision chips  

作　　者：SHI Cong YANG Jie WU NanJian WANG ZhiHua 

机构地区：[1]State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences [2]Department of Electronic Engineering,Tsinghua University [3]Institute of Microelectronics,Tsinghua University

出　　处：《Science China(Information Sciences)》2014年第6期207-218,共12页中国科学（信息科学）（英文版）

基　　金：supported by National Natural Science Foundation of China(Grant Nos.60976023,61234003);Special Funds for Major State Basic Research Project of China(Grant No.2011CB932902)

摘　　要：This paper proposes a high speed multi-level-parallel array processor for programmable vision chips.This processor includes 2-D pixel-parallel processing element（PE）array and 1-D row-parallel row processor（RP）array.The two arrays both operate in a single-instruction multiple-data（SIMD）fashion and share a common instruction decoder.The sizes of the arrays are scalable according to dedicated applications.In PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal directions.This connection can help to speed up local operations in low-level image processing.On the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array.The array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED algorithm.The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.This paper proposes a high speed multi-level-parallel array processor for programmable vision chips.This processor includes 2-D pixel-parallel processing element（PE）array and 1-D row-parallel row processor（RP）array.The two arrays both operate in a single-instruction multiple-data（SIMD）fashion and share a common instruction decoder.The sizes of the arrays are scalable according to dedicated applications.In PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal directions.This connection can help to speed up local operations in low-level image processing.On the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP array.The array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED algorithm.The results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.

关 键 词：vision chip array processor multi-level-parallel high speed image processing face detection 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]