A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS  

作　　者：吕伟 罗多纳 梅逢城 杨家琪 姚立斌 贺林 林福江 

机构地区：[1]Department of Electronic Science and Technology, University of Science and Technology of China [2]Kunming Institute of Physics

出　　处：《Journal of Semiconductors》2014年第5期98-104,共7页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61204033);the Natural Science Foundation of Jiangsu Province(No.BK2012214)

摘　　要：This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.This paper presents a 0.6 V 10 bit successive approximation register （SAR） ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120 × 300 μm^2.

关 键 词：SAR ADC monotonic switching common mode stabilizer comparator offset 

分 类 号：TN432[电子电信—微电子学与固体电子学]