A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications  

作　　者：李弦 钟汇才 贾宬 李鑫 

机构地区：[1]Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2014年第5期105-109,共5页半导体学报（英文版）

摘　　要：A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.A 4-kbit low-cost one-time programmable （OTP） memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor （1.5T） OTP cell is 2.13 μm2, which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch （HVSW） circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification （RFID） tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm2. The 4-kbit OTP macro only consumes 200 × 260 μm^2. The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores.

关 键 词：OTP 1.5 transistor cell high voltage switch RF1D size reduction 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TP368.1[自动化与计算机技术—计算机科学与技术]