A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC  

作　　者：刘术彬 朱樟明 杨银堂 刘帘曦 

机构地区：[1]School of Microelectronics, Xidian University

出　　处：《Journal of Semiconductors》2014年第5期110-117,共8页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.61234002,61006028);the National High-Tech Program of China(Nos.2012AA012302,2013AA014103);the PhD Programs Foundation of Ministry of Education of China(No.20120203110017)

摘　　要：A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.

关 键 词：SHA-less ADC dynamic comparator high speed low offset low power transmission gate 

分 类 号：TN792[电子电信—电路与系统]