A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC  

作　　者：岳森 赵毅强 庞瑞龙 盛云 

机构地区：[1]School of Electronic Information Engineering, Tianjin University

出　　处：《Journal of Semiconductors》2014年第5期118-123,共6页半导体学报（英文版）

基　　金：supported by the National Science and Technology Major Project of China(No.2012ZX03004008)

摘　　要：A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.

关 键 词：sample/hold circuit pipeline ADC gain-boosted OTA bootstrapped switch 

分 类 号：TN792[电子电信—电路与系统] S15[农业科学—土壤学]