基于准循环双对角阵的LDPC码编码算法  

Study on encoding algorithms for QC-LDPC codes with dual-diagonal parity check matrix

作　　者：刘冬培[1] 刘衡竹[1] 张波涛[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2014年第2期156-160,共5页Journal of National University of Defense Technology

基　　金：国家自然科学基金资助项目(60970037)

摘　　要：针对校验矩阵形如准循环双对角阵的结构化LDPC码,对比研究了两类高效的编码算法:矩阵分解编码算法和分项累加递归编码算法,证明了两类算法从实现角度是等价的,但分项累加递归编码算法推导更为直观,且便于硬件并行实现。基于分项累加编码算法,提出了一种适合准循环双对角LDPC码的部分并行编码结构,设计实现了IEEE 802.11n标准中的LDPC码编码器。FPGA实现结果表明,所设计的LDPC编码器具有硬件开销较小、吞吐率高的优点,在码长为1944bit、码率为5/6时信息比特吞吐率最高可达13Gbps。The encoding algorithms of the LDPC codes with quasi-cyclic dual-diagonal parity check matrix were studied. It is demonstrated that the matrix decomposition encoding algorithm and the cumulative recursion encoding algorithm are equivalent for implementation. The cumulative recursion encoding algorithm is straightforwardly facilitated to hardware implementation. Besides,a partly parallel encoding architecture for the QCLDPC codes with dual-diagonal parity check matrix was proposed and a LDPC encoder compatible with IEEE 802. 11n standard was designed. FPGA implementation results show that the hardware overhead of the proposed LDPC encoder is low and the throughput is high. The encoding throughput can reach up to 13Gbps with code length 1944-bit and rate 5 /6.

关 键 词：LDPC码 准循环双对角矩阵 编码算法 部分并行编码结构 高吞吐率 

分 类 号：TN47[电子电信—微电子学与固体电子学]