PLL频率合成器中有源环路滤波器的设计与仿真  

Design and Simulation for Active Loop Filter of PLL Frequency Synthesizer

作　　者：任青莲[1] 高文华[1] 郭萍[1] 

机构地区：[1]太原科技大学电子信息工程学院,山西太原030024

出　　处：《山西电子技术》2014年第2期3-5,共3页Shanxi Electronic Technology

基　　金：2011年山西省高等学校教学改革项目;电工电子现代实验教学体系的研究与实践(J2011067)

摘　　要：为提高PLL频率合成器的性能,简化环路滤波器的设计过程,提出了PLL频率合成器中有源环路滤波器的一种设计方法。首先给出一种实用的三次特性的有源环路滤波器结构,根据电路结构求出其频率特性,结合PLL频率合成器中鉴相器-VCO-分频器的相位传递函数,确定使系统稳定的相位最大返回处频率,合理分配滤波器的零、极点,进而综合出环路滤波器的设计方法,以及电路中各元件的计算公式。文中给出了设计实例并进行了PSPICE仿真,结果表明其性能完全能达到设计要求。In order to improve the performance of PLL frequency synthesizer and simplifies the active loop filter design,a design method is presented in the article. Firstly,it gives the mathematical model of three order active loop filter and calculates its phase transfer function. Secondly,it determines the frequency of phase maximum returning to make the system stable combining with the synthetic phase transfer function in PLL frequency synthesizer,allocates the poles and zeros of filters,and then synthesizes the design method of filter and the formula of circuit component. A design example is given,and its frequency response is simulated based on Pspice. The results show that the performance can completely meet the design requirements.

关 键 词：PLL 频率合成器 有源环路滤波器 相位稳定裕度 PSPICE 仿真 

分 类 号：TN713.1[电子电信—电路与系统]