AES-128算法的FPGA优化实现  

Optimization and Implementation of AES-128 with FPGA

作　　者：何清平[1] 冯锦澎[1] 许百如[1] 

机构地区：[1]广州大学物理与电子工程学院,广东广州510006

出　　处：《中国科技信息》2014年第10期106-108,共3页China Science and Technology Information

摘　　要：针对FPGA的器件资源特点,对AES-128算法进行优化:包括调整轮操作迭代结构获得并行数据路径、用移位寄存器实现ShiftRows运算、用配置Block RAMs实现SubBytes运算、用异或运算和移位运算的资源共享方式实现MixColumns和InvMixColumns运算。最后设计了密钥扩展单元和加/解密单元的FPGA优化实现结构,给出AES-128综合仿真结果。Optimizes and implements the AES- 128 algorithm according to the characteristics of FPGA device resources,including achieving parallel data paths with adjusting the round iteration structure,and replacing the ShiftRows with shift register,and implementing the SubBytes with configuration of the Block RAMs,and expressing the MixColumns and Inv MixColumns with the sharing resource mode by XOR and shift operations.In the end,designs the structure of KeyExpansion unit and Encryption/decryption for FPGA,and gets the result of AES-128 by the synthesis and simulation。

关 键 词：密码体制 信息安全 AES FPGA 

分 类 号：TN918.4[电子电信—通信与信息系统]