一种基于FPGA的CPCI总线接口设计方法  

An interface design method of CPCI bus based on FPGA

作　　者：郭立俊[1] 谭剑波[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,安徽合肥230088

出　　处：《合肥工业大学学报（自然科学版）》2014年第5期596-599,共4页Journal of Hefei University of Technology：Natural Science

摘　　要：在深入研究CPCI总线标准基础上,文章介绍了基于FPGA的CPCI总线接口通信模块设计方法,通过硬件描述语言产生相应的控制时序信号来控制数据总线和地址总线,完成CPCI总线接口通信功能,并利用Signaltap仿真工具验证CPCI总线接口通信的有效性。Based on the study of the compact peripheral component interconnect（CPCI）bus standard,a design method of CPCI bus interface communication module based on field programmable gate array（FPGA）is introduced.The corresponding control timing signal is generated by hardware description language to control the data bus and the address bus,and then the CPCI bus interface communication function is achieved.Finally,the effectiveness of CPCI bus interface communication is validated by Signaltap simulation tools.

关 键 词：FPGA芯片 CPCI总线 桥片 配置寄存器 端口读写 

分 类 号：TP368.2[自动化与计算机技术—计算机系统结构]