一种8位高精度、低功耗DAC设计  

The Design of a 8-bit DAC with High Accuracy and Low Power

作　　者：许波[1] 颜永红[1] 江晓山[2,3] 李怀申[2,3] 王娜[2,3] 

机构地区：[1]湖南大学物理与微电子科学学院,湖南长沙410082 [2]核探测与核电子学国家重点实验室,北京100049 [3]中国科学院高能物理研究所,北京100049

出　　处：《核电子学与探测技术》2014年第2期134-137,151,共5页Nuclear Electronics & Detection Technology

摘　　要：该设计的DAC为芯片内甄别器提供了一个可调的阈值,要求具有较高的精度,较低的功耗。基于chartered 0.35μm工艺,采用Spectre进行了仿真设计,非线性误差DNL<0.025 LSB,INL<0.17LSB,功耗低于3 mW。文章描述了R-2R型DAC的电路结构,主要介绍了电阻网络,抗单粒子翻转的DICE锁存器等的设计。最后给出了版图和后仿结果,满足设计的要求。The DAC is used to provide an adjustable threshold voltage for a discriminator of chip ,the objective is high accuracy and low power .Based on the chartered 0.35μm process,designed and simulated by Spectre ,as a result with nonlinearity error of DNL 〈0.025LSB and INL〈0.17LSB , power under 3 mW.The paper pres-ents the architecture of R -2R Ladder DAC,mainly R-2R ladder topology and DICE latch in details .At last , the layout has been designed and the simulation results have certified in achieving the objective .

关 键 词：数模转换器 R-2R 双互锁存储单元锁存器 积分非线性 差分非线性 匹配 

分 类 号：TN492[电子电信—微电子学与固体电子学]