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作 者:闫亚力[1] 杜会文[1] 杜以涛[1] 郭小文[1]
机构地区:[1]中国电子科技集团公司第四十一研究所,青岛266555
出 处:《国外电子测量技术》2014年第5期48-51,共4页Foreign Electronic Measurement Technology
摘 要:针对复杂频率源的频率分辨率、相位噪声等指标难以同时兼顾的问题,采用多个锁相环组成了多环路结构,利用每一个环路的特点,使频率源输出较好地解决了上述问题。首先对锁相环的基本原理及噪声特性进行了分析,然后依据项目要求给出了包含参考环、高纯环、小数环及YTO环的多环路设计方案,并分别对其中每个环路的设计要点及所起的作用进行了论述。最后通过性能测试,验证了该方案的可行性及先进性,成功实现了宽频带、低相噪及高分辨率等指标,达到了预期的目标。In the complex frequency synthesizer design, it's hard to satisfy the requirements to high frequency resolution and low phase noise. This paper resolves the above-mentioned problem better, by using multi-PLL and taking advantage of the characteristics of each loop. Firstly, the principle and phase noise characteristic of the PLL is analyzed. Then,according to the task of the project,a design scheme based on multi-PLL including reference PLL, high purity PLL , fractional frequency-division PLL and YTO PLL is given. The design essentials and effects of each loop are introduced. Finally, by performance testing, it confirms the feasibility and advantage of this scheme, successfully achieves indexes of wide band, high frequency resolution and low phase noise, and reaches the aim of the design.
分 类 号:TN74[电子电信—电路与系统]
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