A capacitor-free high PSR CMOS low dropout voltage regulator  

作　　者：李志超 刘云涛 旷章曲 陈杰 

机构地区：[1]Institute of Microelectronics,Chinese Academy of Sciences [2]Superpix Micro Technology Co.Ltd

出　　处：《Journal of Semiconductors》2014年第6期109-113,共5页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61036004,61234003,61221004)

摘　　要：This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.This paper presents a capacitor-free CMOS low dropout voltage regulator which has high PSR perfor- mance and low chip area. Pole splitting and gm boosting techniques are employed to achieve good stability. The capacitor-free chip LDO was fabricated in commercial 0.18μm CMOS technology provided by GSMC （Shanghai, China）. Measured results show that the capacitor-free LDO has a stable output voltage 1.79 V, when supply voltage changes from 2.5 to 5 V, and the LDO is capable of driving maximum 100 mA load current. The LDO has high power supply rejection about -79 dB at low frequency and -40 dB at 1 MHz frequency, while sacrifice of the LDO＇s active chip-area is only smaller than 0.02 mm2.

关 键 词：CMOS low dropout regulator power supply rejection CAPACITOR-FREE 

分 类 号：TM44[电气工程—电器] TN912.3[电子电信—通信与信息系统]