A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC  

作　　者：宋毅珺 李文渊 

机构地区：[1]Institute of RF-& OE-ICs,Southeast University

出　　处：《Journal of Semiconductors》2014年第6期123-127,共5页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.61271331);the Jiangsu Provincial PAPD Program

摘　　要：A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.A 6-bit 4 GS/s, high-speed and power-efficient DAC for ultra-high-speed transceivers in 60 GHz band millimeter wave technology is presented. A novel pseudo-thermometer architecture is proposed to realize a good compromise between the fast conversion speed and the chip area. Symmetrical and compact floor planning and layout techniques including tree-like routing, cross-quading and common-centroid method are adopted to guarantee the chip is fully functional up to near-Nyquist frequency in a standard 0.18 #m CMOS process. Post simulation results corroborate the feasibility of the designed DAC, which can perform good static and dynamic linearity without calibration. DNL errors and INL errors can be controlled within 4-0.28 LSB and 4-0.26 LSB, respectively. SFDR at 4 GHz clock frequency for a 1.9 GHz near-Nyquist sinusoidal output signal is 40.83 dB and the power dissipation is less than 37 roW.

关 键 词：high speed DAC CMOS current-steering near-Nyquist sampling 

分 类 号：TN792[电子电信—电路与系统] TH811[机械工程—仪器科学与技术]