一种高CMRR和PSRR的共源共栅放大器  

The high CMRR and PSRR folded-cascode operational amplifier

作　　者：李新[1] 黄璜[1] 王龙[1] 

机构地区：[1]沈阳工业大学信息科学与工程学院,辽宁沈阳110870

出　　处：《电子设计工程》2014年第11期79-83,共5页Electronic Design Engineering

摘　　要：针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共柵放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE-ON40V 1.0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125.8 dB,相位裕度为62.8°,共模抑制比140.9 dB,电源电压抑制比125.5 dB。According to the fact that common mode rejection ratio and power supply rejection ratio are usually low in traditional operational amplifier, a differential input structure of folded-cascode operational amplifier was designed. Two stages of structure was adopted in the design of the whole circuit. The first stage is a differential structure folded cascode amplifier using MOS transistors as the resistors,further increasing the gain ,CMRR, and PSRR of the circuit; The structure of common source amplifier using NMOS as load can dramatically increase the gain and output swing.. Based on LITE-ONdOV 1.0 μm process, the Folded-cascode operational amplifier was designed and simulated by the use of Spectre. The simulation results indicate that the whole circuit can achieve up to 125.8dB gain and 62.8° phase margin . Moreover, the common mode reject ration and power supply rejection ratio are 140.9dB and 25.5dB respectively.

关 键 词：折叠式共源共栅放大器 高增益 共模抑制比 电源抑制比 

分 类 号：TN98[电子电信—信息与通信工程]