基于FPGA的监测接收机中DDC的设计与实现  

Design and realization of DDC for the monitor receiver based on FPGA

作　　者：曾建[1] 冯晓东[1] 

机构地区：[1]重庆邮电大学电信业务支撑系统研究所,重庆400065

出　　处：《微型机与应用》2014年第1期81-83,86,共4页Microcomputer & Its Applications

摘　　要：设计了一种基于FPGA的数字监测接收机中数字下变频的设计方案,详细介绍了数字下变频器中数控振荡器、积分级联梳状滤波器、半带滤波器和FIR滤波器的设计方法,并编写Verilog HDL程序实现各个模块,最后将程序下载到FPGA中测试,得到I/Q信号波形和频谱,能够满足微波数字监测接收机的功能需求。The theories about digital down conversion (DDC) are researched, and a DDC scheme based on field programmable gate array (FPGA) for the digital monitoring receiver is presented, and the detail design of each component of DDC, including numerically controlled oscillator (NCO), cascaded integrator comb (CIC) filter, half-band filter and FIR filter are presented. Each modules of DDC are realized by Verilog HDL program, finally the DDC program is downloaded to FPGA device, and the I/Q signal waveforms outputted by DDC and their frequency spectrum are given. the result shows that the DDC is meted the needs of the microwave digital monitoring receiver.

关 键 词：数字下变频 数控振荡器 积分级联梳状滤波器 FPGA 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置] TN85[自动化与计算机技术—控制科学与工程]