基于FPGA的可配置FFT IP核实现研究  

Research on and Implementation of Reconfigurable FFT IP Core Based on FPGA

作　　者：李大习[1] 

机构地区：[1]江苏自动化研究所计算机事业部,江苏连云港222061

出　　处：《电子科技》2014年第6期46-49,53,共5页Electronic Science and Technology

基　　金：江苏省自然科学基金资助项目(BK2012237)

摘　　要：针对FFT算法基于FPGA实现可配置的IP核。采用基于流水线结构和快速并行算法实现了蝶形运算和4 k点FFT的输入点数、数据位宽、分解基自由配置。使用Verilog语言编写,利用ModelSim仿真,由ISE综合并下载,在Xilinx公司的Virtex-5 xc5vfx70t器件上以200 MHz的时钟实现验证,运算结果与其他设计的运算效率对比有一定优势。A reconfigurable IP core implemented on FPGA is described. This FFT architecture is based on a butterfly process which employs pipeline architecture and fast parallel multiplier. An implementation of 4k points based on this IP with the reconfigurable points, data width and radix is performed. This IP is realized by Verilog and simulated by ModelSim. It is synthesized by ISE and downloaded to Virtex-5 xc5vfx70t that runs at 200 MHz clock. The experi- mental result and performance comparison show that it has better capability and speed than exiting reported realizations.

关 键 词：快速傅里叶变换 可配置 现场可编程门阵列 

分 类 号：TN911.72[电子电信—通信与信息系统]