改进型低纹波Cockcroft-Walton倍压电路及其特性研究  

Advanced Low Ripple Cockcroft-Walton Voltage Multiplier Circuit and Its Characteristics Research

作　　者：李自成[1] 袁保山[2] 

机构地区：[1]成都理工大学工程技术学院,乐山614000 [2]核工业西南物理研究院,成都610041

出　　处：《科学技术与工程》2014年第17期64-67,77,共5页Science Technology and Engineering

基　　金：国家自然科学基金(11375055);国家自然科学基金(11075048);国家自然科学基金(10575033)资助

摘　　要：多级倍压整流器倍压纹波和电压跌落分别受级数次方的影响,在级数增加的情况下会明显增加。在最低级数2倍压电路的基础上,采用移相和反相叠加实现2N倍压电路。使用三相组式变压器输出绕组三相独立连接直流二倍压电路,通过并联输入、串联输出实现6脉周期性叠加,构建12倍压电路。通过叠加,大幅度削弱了脉动的幅度。对纹波和电压跌落进行了理论分析和估算,并与经典型和对称型Cockcroft-Walton多级倍压电路进行比较。结果表明,该电路可以显著减小电压纹波和电压跌落,并明显缩短了输出电压稳态建立的时间。The ripple voltage and voltage drop of multilevel voltage multiplier are affected by the 2th or 3nd power of stage number respectively. In the case of increasing in the stage, the ripple voltage and voltage drop would significantly increase. On the basis of the lowest level voltage double circuit, using shift and the phase superposi- tion 2N time voltage multiplier circuit was realized. By using three-phase independent connection group of three- phase transformer, output winding is connected to DC double voltage circuit. 12 times voltage circuit is built by parallel input, serial output to realize 6 pulses periodic superposition. Through the overlay, the pulsating amplitude is greatly weakened. The theoretical analysis and estimation is made for ripple and voltage drop, and comparison to the typical and symmetrical Cockcroft-Walton multistage voltage multiplier circuit is carried out. Results show that the circuit can significantly reduce the voltage ripple and voltage drop, and significantly reduce the output voltage steady set-up time.

关 键 词：倍压电路 Cockcroft—Walton电路 纹波 电压跌落 移相叠加 CWVM 

分 类 号：TN35[电子电信—物理电子学]