基于Nios Ⅱ的SPI接口实现  

Implementation of SPI Interface Based on Nios Ⅱ

作　　者：康宾[1] 孙亮[2] 周玉娟[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]解放军理工大学,江苏南京210007

出　　处：《计算机与网络》2014年第11期55-58,共4页Computer & Network

摘　　要：Nios Ⅱ是Altera公司的第二代FPGA嵌入式处理器,和其挂接的外围接口相当于一个完整的SOPC系统,AD9517-1ABCPZ是一款时钟芯片,需通过SPI接口配置,让其先于系统的其他部分工作,为系统其它芯片提供时钟。针对SPI接口的实现,目前有很多方法,基于Nios II实现,具有简单灵活、开发周期短、成本低和系统维护方便等优点,可应用于许多中、低速系统设计。实现主要包括硬件设计和软件设计,硬件设计包括基于Nios II的SOPC系统的搭建,SPI-MASTER接口FPGA程序设计;软件设计包括SPI读写函数设计,AD9517-1ABCPZ寄存器配置函数设计。The Nios II is the second generation of FPGA embedded processor of Altera company and links with the peripheral interface to construct a complete SOPC system. AD9517-1ABCPZ is a clock chip, which is configured through SPI interface to operate prior to other parts of system and provide the clock for other chips of system. The implementation of SPI interface can use many methods, and the one adopted in this paper is based on Nios II. This method has the advantages such as simple and flexible operation, short development cycle, low cost as well as easy maintenance systems, etc., which can be applied to various intermediate-speed and low-speed system design. The implementation method mainly includes hardware and software design, the hardware design includes the construction of SOPC system based on Nios II and the design of SPI-MASTER interface FPGA program;the software design includes the design of SPI read-write functions and the design of AD9517-1ABCPZ register configuration functions.

关 键 词：NIOS II SPI FPGA SOPC 

分 类 号：TP334.7[自动化与计算机技术—计算机系统结构]