WLAN MIMO-OFDM系统DSAP设计与实现  

Design and Implementation of Distributed Systolic Array Processor for WLAN MIMO-OFDM Systems

作　　者：朱勇旭 易芝玲 吴斌[2] 周玉梅[2] 

机构地区：[1]中国移动研究院,北京西城区100053 [2]中国科学院微电子研究所,北京朝阳区100029

出　　处：《电子科技大学学报》2014年第3期353-358,共6页Journal of University of Electronic Science and Technology of China

基　　金：国家科技重大专项(2013ZX03004007-004);国家自然科学基金(61204026)

摘　　要：针对无线局域网(WLAN)多输入多输出和正交频分复用(MIMO-OFDM)系统中矩阵的QR分解预处理的延时问题,提出一种分布式脉动阵列处理器(DSAP)进行QR分解预处理。该处理器通过脉动阵列边界单元和内部单元中流水线CORDIC计算,实现子载波信道矩阵的QR分解分布式处理,不同子载波QR分解分布于脉动阵列边界单元和内部单元中CORDIC流水线计算的不同级。与串行脉动阵列处理器(SSAP)相比,在复杂度几乎没有增加情况下,DSAP结构充分利用时钟周期,分解延时约为SSAP结构的8%。在SMIC 0.18μm CMOS工艺下,该分布式脉动阵列结构应用于2发2收MIMO-OFDM数模混合芯片中,芯片测试验证结果表明,数据处理延时能有效减少。To reduce the delay of QR-decomposition in WLAN （wireless local area network） MIMO-OFDM （multiple input multiple output and orthogonal frequency division multiplexing） systems, a distributed systolic array processor （DSAP） is proposed. The structure uses the coordinate rotation digital computer （CORDIC） in the boundary and internal cells of systolic array, and distributes the QR-decomposition of different sub-carriers into the different stages of the pipelining operation of CORDIC in systolic array. Compared with serial systolic array processor （SSAP）, the clock periods can be put to great use in the DSAP, and the delay is reduced by 92%with the same complexity. In SMIC 0.18 μm CMOS technology, a ＆#215;22 analog -digital mixed MIMO-OFDM chip with DSAP has been implemented, and the test results show that it can reduce the delay of data processing effectively.

关 键 词：分布式脉动阵列处理 低延时 MIMO-OFDM QR分解 

分 类 号：TN911[电子电信—通信与信息系统]