FPGA上实现CRC16纠错编码并行计算的探讨  

Exploration for parallel computing of CRC16 checksum on FPGA

作　　者：宁平 

机构地区：[1]上海航天电子技术研究所,上海201109

出　　处：《计算机工程与科学》2014年第6期1023-1027,共5页Computer Engineering & Science

摘　　要：针对以往效率较低的串行计算CRC16CCITT校验码的算法,研究了其计算效率低下的原因,并引入了一种通用的并行算法。在Quartus II下使用Verilog HDL实现了该算法并进行了仿真,使用Nios II自定义指令分析了采用并行算法对串行算法的性能改进。最后,通过多级流水线技术对基本并行电路进行改进和仿真,揭示了利用流水线技术提高存在反馈结构的逻辑电路Fmax存在的问题,并提出了应对的方法。仿真的结果表明,采用改进后的多级流水线电路可以大幅提高并行计算电路Fmax,进而提升CRC16CCITT校验码计算的效率。For the past low efficient serial algorithm of CRC16 CCITT checksum,the reason of calculation inefficiency is studied and a general purpose parallel algorithm is introduced.The parallel algorithm is realized by Verilog HDL and simulated under the Quartus Ⅱ.The Nios Ⅱ custom instruction is used to show the performance improvement of the parallel algorithm in comparison to the serial algorithm.Finally,the basic parallel circuit is improved by means of multilevel pipeline technology and is simulated under Quartus Ⅱ.The results reveal the problems of using pipeline technology to enhance the logic circuit F with feedback structure,so a new method is also proposed in order to solve the problem.The simulation results show that the improved circuit with multi-stage pipeline can significantly increase the circuit Fmax and the computing efficiency of the CRC16 CCITT checksum is also improved.

关 键 词：流水线 并行计算 CRC16 CCITT校验 最高时钟频率 

分 类 号：TN919.33[电子电信—通信与信息系统]