Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system  

作　　者：LIU LeiBo CHEN YingJie YIN ShouYi ZHOU Li YUAN Hang WEI ShaoJun 

机构地区：[1]Institute of Microelectronics,Tsinghua University [2]Institute of Microelectronics of Chinese Academy of Sciences [3]Beijing Academy of Information Science and Technology

出　　处：《Science China(Information Sciences)》2014年第8期158-171,共14页中国科学（信息科学）（英文版）

摘　　要：In this paper, a TPP （Task-based Parallelization and Pipelining） scheme is proposed to implement AVS （Audio Video coding Standard） video decoding algorithm on REMUS （REconfigurable MUltimedia Sys- tem）, which is a coarse-grained reeonfigurable multimedia system. An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning. Several parallel techniques, such as MB （Macro-Block）- based parallel and block-based parallel techniques, and several pipeline techniques, such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation, for performance improvement of the AVS decoder. Also, most computation-intensive tasks in AVS video standards, such as MC （Motion Compensation）, IP （Intra Prediction）, IDCT （Inverse Discrete Cosine Transform）, REC （REConstruct） and DF （Deblocking Filter）, are performed in the two RPUs （Reconfigurable Processing Units）, which are the major computing engines of REMUS. Owing to the proposed scheme, the decoder introduced here can support AVS JP （Jizhun Profile） 1920x 1088@39fps streams when exploiting a 200 MHz working frequency.In this paper, a TPP （Task-based Parallelization and Pipelining） scheme is proposed to implement AVS （Audio Video coding Standard） video decoding algorithm on REMUS （REconfigurable MUltimedia Sys- tem）, which is a coarse-grained reeonfigurable multimedia system. An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning. Several parallel techniques, such as MB （Macro-Block）- based parallel and block-based parallel techniques, and several pipeline techniques, such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation, for performance improvement of the AVS decoder. Also, most computation-intensive tasks in AVS video standards, such as MC （Motion Compensation）, IP （Intra Prediction）, IDCT （Inverse Discrete Cosine Transform）, REC （REConstruct） and DF （Deblocking Filter）, are performed in the two RPUs （Reconfigurable Processing Units）, which are the major computing engines of REMUS. Owing to the proposed scheme, the decoder introduced here can support AVS JP （Jizhun Profile） 1920x 1088@39fps streams when exploiting a 200 MHz working frequency.

关 键 词：AVS video decoder coarse-grained reconfigurable multimedia system computation-intensive tasks parallelization and pipelining HW/SW partitioning 

分 类 号：TN919.81[电子电信—通信与信息系统] TP391[电子电信—信息与通信工程]