A 2.4 GHz low power CMOS transceiver for LR-WPAN applications  

作　　者：LIU WeiYang CHEN JingJing LIU XiaoDong WANG HaiYong WU NanJian 

机构地区：[1]State Key Laboratory for Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences

出　　处：《Science China(Information Sciences)》2014年第8期187-199,共13页中国科学（信息科学）（英文版）

基　　金：financially supported by National Science and Technology Major Project of China (Grant No.2012ZX03004007-002);National Key Technology Research and Development Program of China (Grant No.2012BAH20B02)

摘　　要：A 2.4 GHz low power transceiver for low-rate wireless personal area network （LR-WPAN） appli- cations is presented. The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer, and an adaptive analog baseband to reduce power and area. It achieves -94 dBm of sensitivity, -9 dBm of IIP3 and 28 dBc of image rejection. The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a ＋3 dBm output power. The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves -107.8 dBe/Hz at 1 MHz offset. An ultra-low power nonvolatile memory is used to store configuration data and save power. The chip is implemented in a 0.18 μm CMOS process, and the area is less than 2.8 mm2. The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode.A 2.4 GHz low power transceiver for low-rate wireless personal area network （LR-WPAN） appli- cations is presented. The optimized low-IF receiver consists of a novel current reuse RF front-end with an inductor-less-load balun LNA and quadrature mixer, and an adaptive analog baseband to reduce power and area. It achieves -94 dBm of sensitivity, -9 dBm of IIP3 and 28 dBc of image rejection. The phase-locked loop based direct phase modulated transmitter is proposed to reduce power and deliver a ＋3 dBm output power. The phase noise of the low power frequency synthesizer with current reuse stacked LC-VCO achieves -107.8 dBe/Hz at 1 MHz offset. An ultra-low power nonvolatile memory is used to store configuration data and save power. The chip is implemented in a 0.18 μm CMOS process, and the area is less than 2.8 mm2. The transceiver consumes only 10.98 mW in the receiving mode and 13.32 mW in the transmitting mode.

关 键 词：CMOS current reuse direct modulation LOW-IF low power LR-WPAN 

分 类 号：TN859[电子电信—信息与通信工程]