Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor  

作　　者：LIU LeiBo CHEN YingJie WANG Dong YIN ShouYi WANG Xing WANG Long LEI Hao CAO Peng WEI ShaoJun 

机构地区：[1]Institute of Microelectronics,Tsinghua University [2]Beijing Academy of Information Science and Technology [3]School of Electronic and Information Engineering,Xi'an Jiaotong University [4]National ,ASIC System Engineering Research Center,Southeast University

出　　处：《Science China(Information Sciences)》2014年第8期208-221,共14页中国科学（信息科学）（英文版）

基　　金：supported in part by China National High Technologies Research Program (Grant No.2012AA012701);Tsinghua Information S&T National Lab Creative Team Project;International S&T Cooperation Project of China (Grant No.2012DFA11170);NNSF of China (Grant No.61106022)

摘　　要：This paper proposes a task-based hybrid parallel and hybrid pipeline （THPHP） scheme to implement multi-standard video algorithms, including MPEG-2, H.264, and audio video coding standard （AVS）, on a heterogeneous coarse-grained reconfigurable processor, called the reconfigurable multimedia system （REMUS）. The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition （HD） video decoding standards. In THPHP, we propose both a task-based hybrid parallel scheme, in which macro-block （MB）-level, block-level, and sub-block-level decoding tasks are parallelized to improve data processing throughput, and a hybrid pipeline scheme, in which slice-level, MB-level, block-level and sub-block-level computations are pipelined to improve efficiency. Computation-intensive tasks, such as motion compensation, intra prediction, inverse discrete cosine transform, reconstruction, and deblocking filter, are implemented on two reconfigurable processing units, which are the core computing engines of REMUS. Thanks to the proposed schemes, the implementations can achieve H.264 high profile （HP） 1920x 1080@30 fps streams, AVS Jizhun profile （JP） 1920× 1080@39 fps streams, and MPEG-2 main profile （MP） 1920× 1080@41 fps streams when working at 200 MHz frequency. Compared with XPP-III （a commercial reconfigurable processor）, when implementing H.264 HD decoding, the performance and energy efficiency on REMUS are improved by 1.81× and 14.3×, respectively.This paper proposes a task-based hybrid parallel and hybrid pipeline （THPHP） scheme to implement multi-standard video algorithms, including MPEG-2, H.264, and audio video coding standard （AVS）, on a heterogeneous coarse-grained reconfigurable processor, called the reconfigurable multimedia system （REMUS）. The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition （HD） video decoding standards. In THPHP, we propose both a task-based hybrid parallel scheme, in which macro-block （MB）-level, block-level, and sub-block-level decoding tasks are parallelized to improve data processing throughput, and a hybrid pipeline scheme, in which slice-level, MB-level, block-level and sub-block-level computations are pipelined to improve efficiency. Computation-intensive tasks, such as motion compensation, intra prediction, inverse discrete cosine transform, reconstruction, and deblocking filter, are implemented on two reconfigurable processing units, which are the core computing engines of REMUS. Thanks to the proposed schemes, the implementations can achieve H.264 high profile （HP） 1920x 1080@30 fps streams, AVS Jizhun profile （JP） 1920× 1080@39 fps streams, and MPEG-2 main profile （MP） 1920× 1080@41 fps streams when working at 200 MHz frequency. Compared with XPP-III （a commercial reconfigurable processor）, when implementing H.264 HD decoding, the performance and energy efficiency on REMUS are improved by 1.81× and 14.3×, respectively.

关 键 词：multi-standard video decoder coarse-grained reconfigurable multimedia system computation-intensive tasks parallelization and pipelining HW/SW partitioning 

分 类 号：TN919.81[电子电信—通信与信息系统]