Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS  

作　　者：陈莹梅 Chen Xuehui Yi Lvfan Wen Guanguo 

机构地区：[1]Institute of RF- & OE-ICs,Southeast University [2]Zhongxing Telecom Equipment Corporation

出　　处：《High Technology Letters》2014年第2期140-145,共6页高技术通讯（英文版）

基　　金：Supported by the National High Technology Research and Development Programme of China(No.2011AA010301);the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029)

摘　　要：Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.Phase locked loop （PLL） is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant. The behavioral level model （BLM） of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper, and the design of PLL based clock and data recovery （CDR） circuit aided with jitter attenuation PLL for SerDes application is also presented. The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop. To simultaneously meet jitter tolerance and jitter transfer specifications defined in G. 8251 of optical transport network （ ITU-T OTN） , an additional jitter attenuation PLL is used. Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17ps and 2.3ps respectively. The core of the whole chip consumes 72mA current from a 1.0V supply.

关 键 词：VERILOG-HDL behavioral level model （ BLM） phase locked loops （ PLL） clock and data recovery （CDR） 

分 类 号：TN432[电子电信—微电子学与固体电子学]