基于CPLD技术的CCD驱动时序产生方法  

A Generating Method of CCD Driving Time Order Based on CPLD Technique

作　　者：常丹华[1] 

机构地区：[1]燕山大学光电子工程系,河北省秦皇岛市066004

出　　处：《仪表技术与传感器》2001年第3期26-28,共3页Instrument Technique and Sensor

摘　　要：文中介绍利用可编程逻辑器件 70 0 0系列设计CCD驱动电路的方法。阐述了逻辑设计原理 ,给出了CPLD实现电路和时序仿真波形 ,验证了CPLD技术的可行性。In this paper, a new method for designing Charge Coupling Device driving circuit using the programable logical device of the 7000 series was introduced. The logical design principle,the realizing circuit of CPLD and its waveform of time order simulation were given in details. Futhermore, the feasibility of CPLD technique was also demonstrated.

关 键 词：CPLD 电荷耦合器件 驱动电路 

分 类 号：TN386.5[电子电信—物理电子学]