基于RISC核的HDTV系统层解码设计  

The RISC-Core Based design of HDTV System Layer Decoding

作　　者：杨伟建[1] 姚庆栋[1] 

机构地区：[1]浙江大学信息与电子工程学系信息与通信工程研究所

出　　处：《信号处理》2001年第3期258-263,共6页Journal of Signal Processing

基　　金：国家自然科学基金(批准号69972043)

摘　　要：嵌入式的ＲＩＳＣ核已经成为系统集成芯片中最为常用的部件，它不仅完成系统基本的控制功能，还承担一定的算法任务。在 ＭＰＥＧ－２ ＭＰ@ ＨＬ集成解码芯片中，一种考虑是采用 ＲＩＳＣ核的控制器完成 ＴＳ流的解复用、系统信息解码、视频和音频的同步控制等。本文以符合ＡＴＳＣ标准的 ＭＰＥＧ－２ＴＳ流解复用和系统信息解码为算法对象，研究在片上指令缓存有限的情况下设计嵌入式ＲＩＳＣ核时，系统层解码的软／硬件协同设计。通过对系统层解码进行的软件仿真，给出了具体的解码流程和相应的仿真结果，为如何分配片上指令和数据Ｃａｃｈｅ提供了参考，这些结论都已被应用到实际的ＨＤＴＶ系统集成解码芯片的设计中。Embedded RISC-core has been. a normal component is SOC(System on Chip) design. It can not only accomplish the fundamotal system task, but implement .certain algorithms. In MPEG-2MP@HL decoder chip, we can use a RISC-core controller to complete the following tasks, such as demultiplexing transport stream, parsing system layer, synchronizing video and audio, etc. Based on the design of demultiplexing and parsing procedure of MPEG-2 tranSPort stream, this paper presents the hardware/software co-design of the embedded RISC core, especially for the limited instruction cache size. After software simulation, this paper presents the detailed decode algorithm and corresponding result, which give reference to cache allocation size on chip. All these achievements have been applied to the practical HDTV chip design.

关 键 词：高清晰度电视 RISC 解码 设计 

分 类 号：TN949.17[电子电信—信号与信息处理]