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出 处:《微电子学》2001年第3期212-215,共4页Microelectronics
摘 要:文章提出了一种采用延迟单元交错耦合压控振荡器 (VCO)和高速双系数前置分频器的锁相环 (PLL)频率合成器设计方法。采用 0 .2 5μm的 CMOS工艺模型 ,在 Cadence环境下模拟 ,在相同级数情况下 ,设计获得的 VCO比传统顺序连接的 VCO速度快 1 .4倍 ;运用动态 D触发器实现的双系数前置分频器 ,最高速度可达 2 GHz。该锁相环频率合成器在 40 0 MHz~ 1 .1 GHz的宽频范围内都能保持良好的相位跟踪特性 ,温度系数为 886ppm/°C,电源反射比为 3.3%WT5”BZ]A high performance frequency synthesizer has been designed A novel technique to implement high speed VCO and frequency divider is presented Simulation with 0 25 μm CMOS process model indicates that the operating frequency of the VCO with cross coupled structure is 40% higher than that obtainable from traditionally sequential connected VCO's And the 23/24 prescaler realized by dynamic D type flip flops can achieve an operating frequency up to 2 GHz The PLL frequency synthesizer using the proposed structure operates from 400 MHz to 1 1 GHz and has a temperature coefficient (TC) of 886 ppm /°C and 3 3 %/V supply sensitivity of free running frequency [WT5HZ]
分 类 号:TN74[电子电信—电路与系统]
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