一种新型的针对SRAM-Based FPGAs的容错方法  

A Novel Fault Tolerant Approach for SRAM-Based FPGAs

作　　者：司派发[1] 徐健[1] 黄维康[1] 

机构地区：[1]复旦大学电子工程系CAT室,上海200433

出　　处：《复旦学报（自然科学版）》2001年第3期326-330,共5页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金资助项目 (6 97730 11)

摘　　要：提出了一种针对基于SRAM型的现场可编程门阵列 (FPGA)的新型容错方法 ,包括一套容错结构以及对应的布线过程 .此方法对可编程逻辑单元 (CLB)和连线资源的代价都予以考虑 ,容错布线过程简单 ,耗时少 .模拟结果还显示 ,该方法与以前的方法比较 。A novel fault tolerant approach for SRAM Based FPGAs is presented. The proposed approach includes a fault tolerant architecture and its related routing procedure. In this approach, the overheads for CLBs and interconnects are considered. Under this novel approach the fault tolerant routing procedure is simple and less time consuming. The simulation results show that the proposed approach has lower overhead than previous by published methods.

关 键 词：现场可编程门阵列 容错布线 容错结构 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]