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机构地区:[1]清华大学电子工程系微波与数字通信技术国家重点实验室,北京100084
出 处:《电子学报》2001年第9期1276-1279,共4页Acta Electronica Sinica
基 金:国家"九五"科技攻关项目(No.0239623)
摘 要:针对锁相环在匀滑含有低频大幅度的抖动和漂移的时钟时有诸如同步和捕捉范围很窄、容易失锁等缺点,提出了一种新的全数字时钟匀滑技术一统计预测法.其主要思想是用一个周期的统计结果来预测下一个周期的处理值.从该方法的原理和性能分析可知,其可有效的匀滑各种抖动和漂移,抖动积累较小,同步和捕捉范围很宽,可以匀滑不同频率的时钟.另外,改进的变周期的统计预测法也可使捕捉时间降到合适的长度,以适用于不同场合.As PLLs have some disadvantages such as the narrow synchronizing and pull-in ranges to smooth clocks with lowfrequency large-amplitude jitter and wander, this paper presents a novel universal digital clock smoothness technique-the counting prognostication method. The key element of this technique is to use counting results in a cycle to prognosticate numbers in the next cycle. Principles and perfomance analyses are given to show that it can efficiently smooth jitter and wander ,jitter accumulation is small, and the synchronizing and the pull-in range is very wide to smooth different frequencies. In addition,for applications in some special circumstances, the cycle varied counting prognostication method is also presented to diminish the capture time.
分 类 号:TN911.8[电子电信—通信与信息系统]
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