低相噪数字锁相频率合成器  

Low Phase Noise Digital PLL Frequency Synthesizer

作　　者：徐光争[1] 王晨[1] 纪宝[1] 

机构地区：[1]华东电子工程研究所,合肥230031

出　　处：《微波学报》1998年第4期314-318,共5页Journal of Microwaves

摘　　要：常规的数字锁相频率合成器具有电路简单，工作稳定可靠等特点，但由于鉴相器的倍增噪声往往比基准源的倍增噪声还要高，因而输出相位噪声较高，不能令人满意。本文提出一种双回路反馈锁相频率合成方案，成功地解决了这个问题，由于有效地抑制了鉴相器的倍增噪声，可获得较低的输出相位噪声。这种方案适用于诸如雷达系统等对频率源相位噪声有较高要求的电子设备。Conventional digital PLL frequency synthesizers are characterized by simplicity,high stability and high reliability- However, it is unsatisfactory that the output phase noise isrelatively high due to the fact that the multiplied noise of the phase detector dominates themultiplied noise of the reference. To solve the problem,a dual-feedback PLL frequency synthesizer ispresented. Since the multiplied noise of the phase detector is effectively restrained, lower outputphase noise may be obtained. This synthesizer is suitable to electronic equipments requiring lowphase noise frequency generators,such as radar.

关 键 词：锁相 频率合成器 噪声 

分 类 号：TN74[电子电信—电路与系统]