超标量、超流水线定点RISC核设计  

The Design of RISC Core by Super-scalar and Super-pipelined Fixed-point Technique

作　　者：韦健[1] 张明[1] 周琼芳[1] 遇岩[1] 姚庆栋[1] 

机构地区：[1]浙江大学信息与通信工程研究所ASIC设计研究室,浙江杭州310027

出　　处：《电路与系统学报》2001年第4期56-60,共5页Journal of Circuits and Systems

基　　金：国家自然科学基金(69872033);浙江省综合信息网技术重点实验室;教育部骨干教师计划资助项目

摘　　要：本文从开发指令级并行度ILP的角度出发,分析了超标量、超流水线处理器的体系结构特点,在此基础上给出了一个定点超标量RISC核设计。该设计采用Top-down设计方法,含三个流水执行单元,指令动态调度,实现非阻塞高速缓存non-blocking-caches机制。By exploiting instruction-level parallelism (ILP), the characteristics of architecture of super-scalar and super-pipelined processors are analyzed. Based on the achievement of research, a design of RISC core by super-scalar and super-pipelined technique is given. According to the proposed design, three pipelined execution units are configured by top-down methodology. Instruction dynamic scheduling and non-blocking-caches mechanism are also implemented.

关 键 词：RISC核 指令 微处理器 电路设计 

分 类 号：TP362[自动化与计算机技术—计算机系统结构]