多比特增量-总和调制器中的降噪环路  

Noise-Reducing Loop in Multi-bit Modulator

作　　者：王正宏[1] 凌燮亭[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《电子学报》2001年第8期1013-1017,共5页Acta Electronica Sinica

摘　　要：在单级多比特增量 总和调制器中 ,量化器的规模是与其比特数成指数增长的 ,当比特数增加时 ,量化器会很快变得难以实现 .本文提出了一种新结构 :降噪环路 (Noise ReducingLoop) ,能够利用较少比特的量化器获得较多比特量化器的效果 ,在获得高信噪比的同时 ,大大地减小了电路规模 .在此基础上应用动态量化 (DynamicQuantiza tion)算法 。In a single-stage multi-bit ∑-Δ modulator, the implementation of the multi-bit quantizer is often size and power consuming. When the bits of the quantizer increase, the scale of the circuit increases exponentially and soon becomes practically impracticable. A new architecture, Noise-Reducing Loop, is proposed. It employs quantizer with only a few bits and achieves much better performance that can only be achieved by using a huge quantizer in the conventional structure. Accompanied with the Dynamic Quantization algorithm, the modulators can trace the change of the input signal and achieve the near optimal performance adaptively.

关 键 词：增量-总和调制器 多比特量化器 动态量化 降噪环路 

分 类 号：TN761[电子电信—电路与系统]