基于RAM存储阵列的并行多通道FIFO设计  

Parallel Multi-Channel FIFO Design Based on RAM Storage Array

作　　者：袁亚鹏 倪伟 郑强强 张多利[1] 宋宇鲲[1] YUAN Ya-peng;NI Wei;ZHENG Qiang-qiang;ZHANG Duo-li;SONG Yu-kun(School of Electronic Science and Applied Physics,Hefei University of Technology,Hefei 230009,China)

机构地区：[1]合肥工业大学电子科学与应用物理学院,安徽合肥230009

出　　处：《微电子学与计算机》2018年第12期27-32,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61106020)

摘　　要：FPGA中Block RAM的块状特性决定了具有读写位宽转换功能的异步FIFO容易存在存储资源浪费.针对这个现象,本文提出一种基于存储阵列的新型并行FIFO结构——多通道FIFO共享多RAM(Multi-channelFIFO sharing Multiple RAM,MFMR).与通用FIFO IP相比,MFMR以仅增加少量通用Slice资源为代价,大幅度降低专有Block RAM(BRAM)存储资源消耗,成倍提升存储资源空间有效利用率,最大可达通用FIFO IP资源利用率的N倍,其中N=max(α,1/α),α是FIFO读位宽与写位宽的比值。The feature of block RAM in FPGA determines that asynchronous FIFO with read-write bit-width conversion is easy to waste of storage resources.To solve this problem,a new parallel FIFO architecture,multichannel FIFO sharing multiple RAM(MFMR),based on Storage array,is proposed in this paper.Compared with the common FIFO IP,MFMR reduces the consumption of proprietary Block RAM(BRAM)storage resource by a small amount of only a few general-purpose slice resources,and multiplies the efficient utilization of storage resources by up to N times the utilization of common FIFO IP resources,in which N=max(α,1/α),whereαis the ratio between the read-bit width and the write-bit width of the FIFO.

关 键 词：并行FIFO 位宽转换 存储阵列 存储浪费 

分 类 号：TN402[电子电信—微电子学与固体电子学]