一种低功耗快速锁定简易锁相式频率合成器  

A Simple Phase Locked Synthesizer with Low Power and Fast Lock

作　　者：李琦[1] 李勇兵 翟江辉[1] 李海鸥[1] 肖功利[1] 张法碧[1] 陈永和 傅涛 LI Qi;LI Yongbing;ZHAI Jianghui;LI Haiou;XIAO Gongli;ZHANG Fabi;CHEN Yonghe;FU Tao(School of Information and Communication ,Guilin University of Electronic Technology,Guilin,Guangxi 541004,P.R.China)

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林514004

出　　处：《微电子学》2018年第6期774-778,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61464003);广西自然科学基金资助项目(2015GXNSFAA139300);桂林电子科技大学研究生教育创新计划资助项目(2017YJCX40)

摘　　要：采用0.5μm CMOS工艺,设计了一种简易锁相式频率合成器。采用"类锁相环"结构,在传统锁相环频率合成器的基础上,去除了电荷泵和低通滤波器。利用鉴频鉴相器的输出结果作为开关信号,控制压控振荡器的工作状态,使压控振荡器的输出信号在第N个周期返回鉴频鉴相器后立即被关断,直到下一个参考时钟周期来临。分析了电路的结构和工作原理,并对每个模块进行了理论分析。该频率合成器能够快速地产生固定的时钟频率,具有结构简单、功耗低、锁定时间短等优点。仿真结果表明,输入参考时钟为4 MHz时,该频率合成器的输出频率为15.96MHz,功耗为2.96mW,锁定时间小于1μs。A simple phase locked synthesizer was designed in a 0.5μm CMOS process.Adopting ‘analogical PLL’structure,this circuit removed the charge pump and low pass loop filter on the basis of traditional synthesizers.The output of PFD (phase and freqfiency detector)was used as the switching signal,which could control the operating states of VCO.When the N-th cycle of VCO's output came back through the PFD,the VCO was cut off immediately.It started to work again until the next reference cycle came.The structure and working principle were analyzed,and theoretical analysis of each module was also given.The synthesizer could generate constant clocks and had the advantages of simple structure,low power consumption and short locking time. Simulation results showed that at 4MHz input reference frequency,the output frequency was 15.96MHz,the power consumption was 2.96mW and the locking time was less than 1μs.

关 键 词：频率合成器 低功耗 锁定时间 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN74