一种基于时间拓展方式的实时采样接收算法  

A real-time sampling and receiving algorithm based on time extension

作　　者：李栋 朱樟明[1] 白文彬 刘马良[1] Dong LI;Zhangming ZHU;Wenbin BAI;Maliang LIU(School of Microelectronics,Xidian University,Xi'an 710071,China)

机构地区：[1]西安电子科技大学微电子学院,西安710071

出　　处：《中国科学：信息科学》2019年第1期104-111,共8页Scientia Sinica(Informationis)

基　　金：国家自然科学基金(批准号:61625403)资助项目

摘　　要：本文提出了一种基于时间拓展方式的实时采样接收算法.该算法利用DTC (digital to time converter)产生两组相位可控的方波信号分别控制基带信号的发射和接收ADC (analog to digital converter)的采样,这两组方波信号之间的相位差为等差数列,通过调整锁相环的倍频比与输入信号的参考频率使其最小相位差为62 ps,从而完成低频ADC (1 MHz)对高频信号的等效采样,由此大大降低系统的功耗和硬件系统的设计难度,增加系统的可维护性.利用Verilog HDL在FPGA (field programmable gate array)上实现了该算法,并完成验证.In this paper, a real-time sampling and receiving algorithm based on time expansion is proposed.The algorithm has been verified by FPGA(field programmable gate array). Two sets of square wave signals, the phases of which can be controlled, are generated by using DTC(digital to time converter) to control the emission of the signal and receiving ADC(analog to digital converter) sampling. The phase difference between the two signals is an arithmetic sequence by adjusting the frequency multiplication ratio of the PLL(phase locked loop)and the reference frequency of the input signal, the minimum phase difference is 62 ps. The high-frequency signal is sampled by low-frequency ADC, which greatly reduces the design difficulty of the system’s power and hardware system, and increases the maintainability of the system. The equivalent sampling frequency can reach 16 GS/s.The algorithm is implemented on FPGA with Verilog HDL, and the verification is completed.

关 键 词：时间拓展 DTC 等效采样 FPGA 

分 类 号：TN79[电子电信—电路与系统]