基于AMBA的AHB总线矩阵设计  

AHBBus Matrix Design Based on AMBA

作　　者：王一楠 林涛[1] 余宁梅[1] WANG Yi-nan;LIN Tao;YU Ning-mei(Xi'an University of Technology,School of automation and information engineering,Xi'an,710048,China)

机构地区：[1]西安理工大学自动化与信息工程学院,陕西西安710048

出　　处：《微电子学与计算机》2019年第2期73-77,共5页Microelectronics & Computer

基　　金：陕西省自然科学基础研究计划资助项目(2017JM6042)

摘　　要：本文设计了一种能够兼容AMBA主从设备的AHB总线矩阵,旨在实现多个主设备并行访问多个从设备,并且提高带宽,减少多路主机访问从机时产生的延迟.对主体架构和微架构进行描述,详述了各模块的设计思路,并通过Verilog HDL对所设计的总线系统进行了RTL行为级描述,并通过参数化设计,实现从机地址和总线支持主从机数量可配.最后搭建测试环境,对所设计的总线系统基本功能进行测试,证明8组主设备输入的情况下,在多主设备交叉访问多从设备的测试条件下,相比于传统AHB总线,AHB总线矩阵最多可减少3倍总线访问延迟、增加8.5倍总线吞吐量.In this paper,an AHB Matrix bus system which is compatible with AMBA master and slave devices is designed,aiming at realizing multiple master devices to access multiple slave devices in parallel.This bus system can effectively improve the bandwidth and reduce the delay caused by multiple master accessing the slave.Its main structure and micro-architecture is elaborated with the design ideas of each module.The bus system is implemented with Verilog HDL in RTL behavior level.Slave address and master/slave number supported can be configurable via parameterized design.Finally,the verification environment is set up to test the basic functions of the bus matrix.It is proved that in the testcase of the 8 masters inputs,Compared with the traditional AHB bus,the AHB bus matrix under the condition of multiple masters cross-access multiple slaves can reduce the bus access delays up to 3 times and increase the bus throughput by 8.5 times.

关 键 词：AMBA总线协议 并行访问 AHB总线矩阵 

分 类 号：TP36811[自动化与计算机技术—计算机系统结构]