基于FC协议的PCS层设计和协议分析仪验证  

Design and protocol analyzer verification of the physical coding sublayer based on the FC protocol

作　　者：杨钞翔 孔宪伟 栾文焕 张远航[1] 王志军 张春[1] 王自强[1] YANG Chao-xiang;KONG Xian-wei;LUAN Wen-huan;ZHANG Yuan-hang;WANG Zhi-jun;ZHANG Chun;WANG Zi-qiang(Institute of Microelectronics,Tsinghua University,Beijing 100084,China;Key Laboratory of Integrated Circuits Testing and Evaluation,Ministry of Industry and Information Technology,Beijing 100176,China)

机构地区：[1]清华大学微电子学研究所,北京100084 [2]中国电子技术标准化研究院集成电路测试与评价工业和信息化部重点实验室,北京100176

出　　处：《微电子学与计算机》2019年第3期7-11,共5页Microelectronics & Computer

基　　金：国家科技重大专项(2016ZX01012101)

摘　　要：FC光纤通道协议作为新一代重要总线技术,具有带宽高、扩展性强、可靠性强、实时性强、支持多种媒介、抗电磁干扰等优良特点,发展迅速并在诸多领域得到了广泛应用.本文针对FC协议的PCS层进行深入研究,解析其关键模块:弹性缓冲器、8B/10B编解码器、位宽变换器、同步器等,提出整体设计架构,使用verilog语言完成代码设计,搭建回环验证平台,并采用FC专用协议分析仪,结合FPGA进行验证,完成设计.As an important new generation of bus technology, the Fibre Channel protocol has the excellent features of high bandwidth, strong scalability, high reliability, real-time performance, supporting for multiple media, and immunity to electromagnetic interference. It has developed rapidly and has been widely used in many fields. This article carries on the thorough research to the PCS layer of the FC protocol, and analyzes its key modules: elastic buffer, 8 B/10 B codec, bit-width converter, synchronizer, etc. And it proposes an overall design architecture, uses verilog language to complete code design, builds a loopback verification platform, and uses the FC protocol analyzer, combined with FPGA verification to complete the design.

关 键 词：FC协议 PCS层 协议分析仪 FPGA验证 

分 类 号：TN492[电子电信—微电子学与固体电子学]